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Dual RF LDMOS Bias Controllers
with I 2 C/SPI Interface
V DACOUT = × LOCODE + × [ HICODE ? LOCODE ] ×
2 2 2 10
Analog-Input Protection
Internal ESD protection diodes clamp all analog inputs
to AV DD and AGND, allowing the inputs to swing from
AGND - 0.3V to AV DD + 0.3V without damage. If an
analog input voltage exceeds the supplies, limit the
input current to 2mA.
DAC Description
The MAX1385/MAX1386 include two 8-bit and 10-bit
DAC blocks to independently control the voltage on
each LDMOS gate. Both 10-bit and 8-bit DACs can be
automatically calibrated to minimize output error over
time, temperature, and supply voltage. The 8-bit and
10-bit DACs have unipolar transfer functions and have
a relationship to the output voltage by the following
equation:
V REF V REF FINECODE
8 8
where LOCODE, HICODE, and FINECODE are the low
wiper (8 bits), high wiper (8 bits), and fine DAC (10 bits)
values written to the DAC by the user. LOCODE,
HICODE, and FINECODE represent the values in the
DAC input registers and may or may not be the actual
values in the DAC output registers depending whether
autocalibration is used or not (see the 8-Bit Coarse-
DAC Adjustment section). To find the actual voltage at
GATE_, multiply the V DACOUT result by 2 (MAX1385) or
4 (MAX1386). Due to the buffer amplifiers, the voltage
at GATE_ cannot be set below 100mV above AGND. It
is recommended that the LOCODE for DAC1 and DAC2
are set so that the minimum possible output at GATE_
is 200mV (MAX1385) and 400mV (MAX1386).
The DACs can be operated to produce an 18-bit
monotonic DAC with 12-bit (typ) INL. Write to either
HICODE or LOCODE in a leapfrog fashion, without
commanding autocalibration, to configure the 18-bit
monotonic DAC. When LOCODE > HICODE, invert the
value of FINECODE.
8-Bit Coarse-DAC Adjustment
Each DAC control block contains a resistor string with
wipers that serve as an 8-bit coarse DAC. Wipers are
set by writing to the appropriate DAC input registers
and/or using the Load DAC Control register (LDAC)
commands. The output of a coarse DAC is not updated
until the appropriate DAC output register(s) have been
set. See Figure 5 for the relationship between DAC
input registers, DAC output registers, and wipers.
DAC output registers are not directly accessible to the
user. Choose which input register to write to based on
whether automatic low or high calibration is desired, or
if updates to the output of the DAC need to be initiated
immediately. In the case of automatic low or high cali-
bration, a correction code is added to or subtracted
from the 10-bit fine-DAC input register. Transfers from
the DAC input registers to DAC output registers can
occur immediately after a write to the appropriate DAC
input register or on a software command through the
Software LDAC register. See the Register Descriptions
section for bit-level descriptions of these registers.
10-Bit Fine-DAC Adjustment
Each DAC control block contains a 10-bit fine DAC that
operates between the high and low wiper positions
from the 8-bit coarse DAC. The 10-bit fine DAC also
has an optional automatic calibration mode and can be
updated immediately or on a software-issued command
in the Software LDAC register. Writing to the appropri-
ate fine-DAC input register determines whether auto-
matic calibration is used and/or when the DAC is
updated. See Figure 6 for the relationship between
DAC input registers, DAC output registers, and the
Software LDAC register.
The fine-DAC output registers are not directly accessi-
ble. Choose which DAC input register to write to based
on whether automatic fine calibration is desired, or
whether updates to the output of the DAC need to be ini-
tiated immediately. In the case of automatic fine calibra-
tion, a correction code is added to or subtracted from
the input register code and transferred to the appropriate
fine-DAC output register. Transfers from a fine-DAC input
register to a fine-DAC output register can occur immedi-
ately after a write to the appropriate DAC input register or
on a software command through the Software LDAC reg-
ister. See the Register Descriptions section for bit-level
detail of these registers.
______________________________________________________________________________________
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